This invention relates to first-in-first-out (FIFO) memory devices and more particularly to a display FIFO module that issues requests for display data to a dynamic random access memory (DRAM) controller sequencer which prioritizes DRAM access requests received from various modules.
In a DRAM interface, as shown in FIG. 1, a plurality of modules, including a display FIFO module 12, a CPU 14, a BitBLT engine module 16, a half frame buffer logic module 18, and other modules, such as an nth module 20 are connected to a DRAM controller sequencer 22, which decides which one of the modules should be granted access to a DRAM 24. The BitBLT engine module controls block transfer of bitmap images to, from or within the DRAM. The half frame buffer logic module supports display on a dual scan LCD panel. A DRAM address generator 52 is connected to DRAM controller sequencer 22 and display FIFO module 12. The DRAM address generator generates DRAM addresses to the DRAM controller sequencer. A CRT controller 50 controls DRAM address generator 52 and display pipeline 27. The CRT controller instructs the DRAM address generator when to start loading the FIFO. Display FIFO module 12 is connected between the DRAM controller sequencer 22 and a display pipeline 27 which is connected to a display device 26 such as a cathode ray tube (CRT) or liquid crystal display (LCD). Display FIFO module 12 is used for receiving and storing display data for the display device. When a FIFO in the display FIFO module is used to store display data received from DRAM 24, sometimes FIFO overrun may occur in which new data transferred to the FIFO exceeds its capacity so that some unread data in the FIFO will be overwritten by the new data. Also, FIFO underrun may occur when the FIFO runs out of display data and unintended data will be displayed on the display device. It is imperative to prevent both FIFO overrun and underrun conditions from occurring. At the same time, it is also desirable to improve the efficiency of the interaction between the various modules connected to the DRAM controller sequencer and the display FIFO module. For example, the CPU should not have to wait long for DRAM access while the display FIFO module is being serviced by the DRAM controller sequencer.
In devices such as that shown in FIG. 1, display FIFO module 12 issues a low priority request when the FIFO is ready to accept new data without overwriting unread data. The display FIFO module issues a high priority request when the FIFO must receive new data or FIFO underrun will occur. These requests are granted on a priority basis along with requests from the CPU and BitBLT engine requests as disclosed and described in U.S. Pat. Nos. 5,673,416 and 5,767,866, for example.
In certain prior art devices, due to the nature of the DRAM requests and the priority scheme used, there are long waiting periods during which the CPU has to wait for DRAM access. This results in inefficient CPU operations and slows down the computer system. This problem was addressed in U.S. Pat. No. 5,673,416 by increasing the time during which the low priority request is active. However, this can result in repetitive display FIFO requests as the FIFO data level oscillates around the low priority request threshold with the request being removed as the FIFO is filled above the threshold and then being reasserted as soon as the level drops below the threshold. In low power devices such as "hand-held" PCs, the resulting frequent memory accesses can be a significant power drain.
The inventor addressed this circumstance in Ser. No. 09/118,212 by maximizing the use of long burst DRAM access, which effectively minimizes the time used to access the DRAM and maximizes idle periods between accesses. In the invention of the '212 application the low priority request is issued when the FIFO data level falls below or is equal to the high threshold value and is de-asserted when the FIFO level is greater than a predetermined low threshold value. The hysteresis effect exhibited by the low priority request prevents it from being immediately re-asserted as soon as the FIFO level falls to the low threshold and prevents oscillation of the FIFO level about the low threshold value. In earlier devices, this oscillation translates into numerous requests for single memory accesses. The introduction of hysteresis on the low priority request results in the FIFO being emptied to the high priority threshold and eliminates the oscillation. Several single memory accesses are deferred into one long burst of memory access. This can save power in limiting the number of memory transfers (each of which uses power) and can create idle periods in which low-power devices can enter a power-savings mode. These idle periods are beneficial for saving power under certain conditions such as during static display in which there is no CPU activity, no BitBLT activity and no memory activity other than the memory activity required to draw a static image on a display. However, these idle periods or hysteresis time can result in inefficient memory usage during other conditions such as when there is BitBLT activity.
The FIFO low priority threshold is, heretofore, preset and is system specific. It is set to the highest possible value that will prevent FIFO overflow. As an example, assume the FIFO depth is 64. The threshold will be set to 64 minus a "turn-off latency factor". The latency factor is the maximum time it takes to stop filling the FIFO when the FIFO level passes the low threshold. It is system specific and would include such factors as the time required for registering the event of the rising FIFO depth surpassing the low priority threshold, removing the request for memory access, the memory controller acknowledging the removal of the request, and the external RAM completing its current cycle and pumping out the remaining data in its pipeline. With the FIFO low priority threshold set to the highest value that will prevent overrun and the FIFO high priority threshold set to the lowest value that will prevent underrun, the FIFO will first occupy the memory while it fills up by long burst DRAM access. Due to the hysteresis effect discussed above, the display FIFO then releases the memory for a relatively long time.
The hysteresis effect of the display FIFO low request can sometimes have the effect of poor memory utilization where the display FIFO is large and other devices that access the DRAM have a smaller FIFO. For example, the bit block transfer (BitBLT) engine may have a smaller FIFO than the display FIFO. In this situation, the display FIFO will fill up and then release the memory for a long time due to the hysteresis effect of the FIFO low request (i.e. it is not reasserted until the FIFO drops to the high priority threshold). During this long period of display FIFO inactivity, the BitBLT will access the memory. However, if the BitBLT FIFO is relatively small, the BitBLT can use only a portion of the hysteresis time (i.e. period of display FIFO inactivity) since its FIFO will be filled or emptied relatively quickly.